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204pin DDR3 SDRAM SODIMM
DDR3 SDRAM Unbuffered SODIMM Based on 2Gb M version
HMT451S6MMP(R)8C
** Contents are subject to change without prior notice.
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HMT451S6MMP(R)8C
Revision History
Revision No. 0.1 0.2 History Initial Release IDD Update Draft Date Oct. 2008 Apr. 2009 Remark
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HMT451S6MMP(R)8C
Table of Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 4GB, 512Mx64 Module(2Rank of x8) 4. Absolute Maximum Ratings 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Range 5. AC & DC Operating Conditions 5.1 Recommended DC Operating Conditions 5.2 DC & AC Logic Input Levels 5.2.1 For Single-ended Signals 5.2.2 For Differential Signals 5.2.3 Differential Input Cross Point 5.3 Slew Rate Definition 5.3.1 For Ended Input Signals 5.3.2 For Differential Input Signals 5.4 DC & AC Output Buffer Levels 5.4.1 Single Ended DC & AC Output Levels 5.4.2 Differential DC & AC Output Levels 5.4.3 Single Ended Output Slew Rate 5.4.4 Differential Ended Output Slew Rate 5.5 Overshoot/Undershoot Specification 5.5.1 Address and Control Overshoot and Undershoot Specifications 5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications 5.6 Input/Output Capacitance & AC Parametrics 5.7 IDD Specifications & Measurement Condtiions 6. Electrical Characteristics and AC Timing 6.1 Refresh Parameters by Device Density 6.2 DDR3 Standard speed bins and AC para 7. DIMM Outline Diagram 7.1 4GB, 512Mx64 Module(2Rank of x8)
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1. Description
This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 2Gb M version. DDR3 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM series based on 2Gb M ver. provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
* VDD=VDDQ=1.5V * VDDSPD=3.0V to 3.6V * Fully differential clock inputs (CK, /CK) operation * Differential Data Strobe (DQS, /DQS) * On chip DLL align DQ, DQS and /DQS transition with CK transition * DM masks write data-in at the both rising and falling edges of the data strobe * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported * Programmable additive latency 0, CL-1 and CL-2 supported * Programmable CAS Write latency (CWL) = 5, 6, 7, 8 * Programmable burst length 4/8 with both nibble sequential and interleave mode * BL switch on the fly * 8 banks * 8K refresh cycles /64ms * DDR3 SDRAM Package: JEDEC standard 82ball FBGA(x4/x8) with support balls * Driver strength selected by EMRS * Dynamic On Die Termination supported * Asynchronous RESET pin supported * ZQ calibration supported * TDQS (Termination Data Strobe) supported (x8 only) * Write Levelization supported * Auto Self Refresh supported * 8 bit pre-fetch
1.1.2 Ordering Information
# of DRAMs 16 16 # of ranks 2 2
Part Name HMT451S6MMP8C-S6/G7* HMT451S6MMR8C-S6/G7*
Density 4GB 4GB
Organization 512Mx64 512Mx64
Materials Lead free Halogen free
*Information on temperature sensor can be found on the label: T0 indicates that the DIMM has temperature sensor. N0 indicates that the DIMM does not have temperature sensor.
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1.2 Speed Grade & Key Parameters
MT/S Grade tCK (min) CAS Latency tRCD (min) tRP (min) tRAS (min) tRC (min) CL-tRCD-tRP DDR3-800 -S6 2.5 6 15 15 37.5 52.5 6-6-6 DDR3-1066 Unit -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 ns tCK ns ns ns ns tCK
1.3 Address Table
4GB Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 512M x 64 8K/64ms A0-A14 A0-A9 BA0-BA2 1KB 2 16
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2. Pin Architecture
2.1 Pin Definition
Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS WE S[1:0] A[9:0], A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Description Clock Inputs, positive line Clock Inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst Stop SDRAM Bank Address On-die termination control 2 2 2 1 1 1 2 14 1 1 3 2 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] RESET TEST EVENT VDD VSS VREFDQ VREFCA VDDSPD Vtt NC Description Data Input/Output Data Masks Data strobes Data strobes complement Reset pin 64 8 8 8 1
Logic Analyzer specific test pin (No 1 connect on SODIMM) Temperature event pin Core and I/O power Ground Input/Output Reference SPD and Temp sensor power Termination voltage Reserved for future use Total 1 18 52 2 1 2 2 204
Serial Presence Detect (SPD) Clock 1 input SPD Data Input/Output SPD address 1 2
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2.2 Input/Output Functional Description
Symbol CK0/CK0 CK1/CK1 Type Polarity Function
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when
Input
Cross point
CKE[1:0]
Input
Active High
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3 SDRAM command decoder when low and disables the
S[1:0]
Input
Active Low
command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1.
RAS, CAS, WE BA[2:0] ODT[1:0]
Input Input Input
Active Low Active High
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which DDR3 SDRAM internal bank of eight is activated. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write
A[9:0], A10/AP, A11, A12/BC, A[15:13]
Input
-
cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly) will be performed (HIGH, no burst chop; LOW, burst chopped)
DQ[63:0] DM[7:0]
In/Out Input
Active High
Data Input/Output pins. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In
DQS[7:0], DQS[7:0]
Write mode, the data strobe is sourced by the controller and is centered in the data
In/Out
Cross Point
window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS.
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Symbol VDD,VDDSPD, VSS, VREFDQ, VREFCA SDA SCL SA[1:0] TEST
Type Supply Supply
Polarity
Function
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. Reference voltage for SSTL15 inputs. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and
In/Out Input Input In/Out Wire OR Out In
Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. Address pins used to select the Serial Presence Detect and Temp sensor base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules (SO-DIMMs). The EVENT pin is reserved for use to flag critical module temperature. A resistor
EVENT RESET
Active Low Active Low
may be connected from EVENT bus line to VDDSPD on the system planar to act as a pullup. This signal resets the DDR3 SDRAM
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2.3 Pin Assignment
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Front Side VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 Back Side VSS DQ4 DQ5 VSS DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 Pin # 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 Front Side DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD Pin # 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 Back Side VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A152 A142 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1 Pin # 105 Front Side VDD Pin # 106 Back Side VDD BA1 RAS VDD S0 ODT0 VDD ODT1 NC VDD Pin # 157 159 161 163 165 167 169 171 173 175 Front Sid DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 Pin # 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 Back Side DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS EVENT SDA SCL VTT
107 A10/AP 108 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 BA0 VDD WE CAS VDD A132 S1 VDD TEST VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS 110 112 114 116 118 120 122 124
126 VREFCA 177 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS 179 181 183 185 187 189 191 193 195 197
83 A12/BC 85 87 89 91 93 95 97 99 101 103 A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0
199 VDDSPD 200 201 203 SA1 VTT 202 204
NC = No Connect; RFU = Reserved Future Use 1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
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3.1 4GB, 512Mx64 Module(2Rank of x8)
A[O:N]/BA[O:N] S0/S1 ODT0/ODT1 CK0 CKE0/CKE1
The SPD may be integrated with the Temp Sensor or may be a separate component
CK1 CK1
RAS
CAS
CK0
WE
DQS0 DQS0 DM0 DQ [0:7]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
D0,D8 (Stacked)
ODT0/ODT1 CK CKE0/CKE1 WE
DQS1 DQS1 DM1 DQ [8:15]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
SCL SA0 SA1
SCL A0 Temp Sensor (with SPD) A1 A2 EVENT EVENT
SDA
D4,D12 (Stacked)
ODT0/ODT1 CK CKE0/CKE1 WE
CS0/CS1
CS0/CS1
SCL SA0 SA1
CAS
RAS
RAS
CAS
SCL A0 A1 A2
(SPD) WP
SDA
CK
CK
Vtt DQS2 DQS2 DM2 DQ [16:23] DQS DQS DM DQ [0:7] 240ohm +/-1% DQS3 DQS3 DM3 DQ [24:31] DQS DQS DM DQ [0:7] 240ohm +/-1% VDDSPD VREFCA VREFDQ VDD VSS
A[O:N]/BA[O:N]
Vtt
SPD/TS D0-D15 D0-D15 D0-D15 D0-D7, SPD, TS D0-D3, D8-D11 D4-D7, D12-D15 D0-D3, D8-D11 D4-D7, D12-D15 D0-D7 D8-D15 D0-D7 D8-D15 D0-D7 D8-D15 Temp Sensor D0-D15
ZQ
ZQ
A[O:N]/BA[O:N]
D1,D9 (Stacked)
ODT0/ODT1 CK CKE0/CKE1 CAS WE
D5,D13 (Stacked)
ODT0/ODT1 CK CKE0/CKE1 WE
CK0 CK1 CK0 CK1 CKE0 CKE1 S0 S1
CS0/CS1
RAS
RAS
CAS
CK
DQS4 DQS4 DM4 DQ [32:39]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
CS
CK
A[O:N]/BA[O:N]
ODT0/ODT1
CKE0/CKE1
CS0/CS1
CS0/CS1
RAS
CAS
CK
ODT0/ODT1
RAS
CK
CK CKE0/CKE1
CAS
WE
A[O:N]/BA[O:N]
D2,D10 (Stacked)
DQS5 DQS5 DM5 DQ [40:47]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
ODT0 ODT1 EVENT RESET
D6,D14 (Stacked)
WE
CK
D4,D12
D5,D13
D6,D14
D7,D15
DQS6 DQS6 DM6 DQ [48:55]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
A[O:N]/BA[O:N]
ODT0/ODT1
CKE0/CKE1
CS0/CS1
CS0/CS1
RAS
CAS
CK
ODT0/ODT1
RAS
WE CK
CK CKE0/CKE1
CAS
A[O:N]/BA[O:N]
D3,D11 (Stacked)
DQS7 DQS7 DM7 DQ [56:63]
DQS DQS DM DQ [0:7]
ZQ
240ohm +/-1%
D7,D15 (Stacked)
WE
V1 D0,D8
D1,D9
D2,D10
D3,D11
CK
NOTES
Address and Control Lines
1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown
Vtt Vtt VDD VDD
Rank 0 Rank 1
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Vtt
V2
V3
V4
Vtt
V1
V2
V3
V4
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4. ABSOLUTE MAXIMUM RATINGS
4.1 Absolute Maximum DC Ratings
Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V - 0.4 V ~ 1.975 V -55 to +100 Units V V V ,2 Notes ,3 ,3
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
4.2 DRAM Component Operating Temperature Range
Symbol TOPER Parameter Normal Temperature Range Extended Temperature Range Rating 0 to 85 85 to 95 Units Notes ,2 1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85... and 95... case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/ or the DIMM SPD for option avail ability. b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
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5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
Rating Min. 1.425 1.425 Typ. 1.500 1.500 Max. 1.575 1.575
Symbol VDD VDDQ
Parameter Supply Voltage Supply Voltage for Output
Units V V
Notes 1,2 1,2
1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
5.2 DC & AC Logic Input Levels
5.2.1 DC & AC Logic Input Levels for Single-Ended Signals DDR3-800, DDR3-1066 Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VRefDQ (DC) VRefCA (DC) VTT Parameter Min DC input logic high DC input logic low AC input logic high AC input logic low Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Termination voltage for DQ, DQS outputs 0.49 * VDD 0.49 * VDD VDDQ/2 - TBD Vref + 0.175 Vref + 0.100 Max Vref - 0.100 Vref - 0.175 0.51 * VDD 0.51 * VDD VDDQ/2 + TBD V V V V V V V 1, 2 1, 2 1, 2 1, 2 3, 4 3, 4 Unit Notes
1. For DQ and DM, Vref = VrefDQ. For input only pins except RESET#, Vref = VrefCA. 2. The "t.b.d." entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef (DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure 5.2.1. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 1. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
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voltage
VDD
VRef ac-noise VRef(DC)
VRef(t) VRef(DC)max VDD/2 VRef(DC)min
VSS
time
< Figure 5.2.1: Illustration of Vref (DC) tolerance and Vref AC-noise limits >
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef (DC), as defined in Figure. This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef (DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
5.2.2 DC & AC Logic Input Levels for Differential Signals
DDR3-800, DDR3-1066 Min + 0.200 Max - 0.200
Symbol VIHdiff VILdiff Note1:
Parameter Differential input logic high Differential input logic low
Unit V V
Notes 1 1
Refer to "Overshoot and Undershoot Specification section 6.5 on 26 page
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5.2.3 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS.
VDD CK#, DQS#
VIX VDD/2 VIX VIX
CK, DQS VSS
< Figure 5.2.3: Vix Definition >
DDR3-800, DDR3-1066 Symbol Parameter Min VIX Differential Input Cross Point Voltage relative to VDD/2 - 150 Max + 150 mV Unit Notes
< Table 5.2.3: Cross point voltage for differential input signals (CK, DQS) >
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5.3 Slew Rate Definitions
5.3.1 For Single Ended Input Signals
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max. - Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min and the first crossing of VRef. Measured Min Vref Vref VIL (DC) max VIH (DC) min Max VIH (AC) min VIL (AC) max Vref Vref
Description Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Input slew rate for falling edge
Defined by VIH (AC) min-Vref Delta TRS Vref-VIL (AC) max Delta TFS Vref-VIL (DC) max Delta TFH VIH (DC) min-Vref Delta TRH
Applicable for
Setup (tIS, tDS)
Hold (tIH, tDH)
< Table 5.3.1: Single-Ended Input Slew Rate Definition >
Part A: Set up Delta TRS Single Ended input Voltage(DQ,ADD, CMD) vIH(AC)min vIH(DC)min
vRefDQ or vRefCA
vIL(DC)max vIL(AC)max
Delta TFS
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P a rt B : H o ld D e lta T R H Single Ended input Voltage(DQ,ADD, CMD) v IH (A C )m in
v IH (D C )m in
v R e fD Q o r v R e fC A
v IL (D C )m a x v IL (A C )m a x D e lta T F H
< Figure 5.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >
5.3.2 Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table and Figure . Measured Min VILdiffmax VIHdiffmin Max VIHdiffmin VILdiffmax
Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Note:
Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
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Differential Input Voltage (i.e. DQS-DQS; CK-CK)
D e lta T R d iff vIH d iffm in
0
vILd iffm a x D e lta T F d iff
< Figure 5.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
Below table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level DDR3-800, 1066 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ Unit V V V V 1 Notes
VTT - 0.1 x VDDQ V 1 (for output SR) 1. The swing of 1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2.
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5.4.2 Differential DC & AC Output Levels
Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) VOLdiff (AC) Parameter AC differential output high measurement level (for output SR) DDR3-800, 1066 + 0.2 x VDDQ Unit V Notes 1
AC differential output low - 0.2 x VDDQ V 1 measurement level (for output SR) 1. The swing of ae 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40Y and an effective test load of 25Y to VTT = VDDQ/2 at each of the differential output
5.4.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 5.4.3. Measured From VOL(AC) VOH(AC) To VOH(AC) VOL(AC)
Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Note:
Defined by VOH(AC)-VOL(AC) DeltaTRse VOH(AC)-VOL(AC) DeltaTFse
Output slew rate is verified by design and characterisation, and may not be subject to production test.
D e lt a T R s e Single Ended Output Voltage(l.e.DQ)
vO H (A C )
V
vO L(A C )
D e lt a T F s e
< Figure 5.4.3: Single Ended Output Slew Rate Definition >
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Parameter Single-ended Output Slew Rate
Symbol SRQse
DDR3-800 Min 2.5 Max 5 2.5
DDR3-1066 Min Max 5
Units V/ns
*** Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) For Ron = RZQ/7 setting < Table 5.4.3: Output Slew Rate (single-ended) >
5.4.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in below Table and Figure 5.4.4 Measured From VOLdiff (AC) VOHdiff (AC) To VOHdiff (AC) VOLdiff (AC)
Description Differential output slew rate for rising edge Differential output slew rate for falling edge
Defined by VOHdiff (AC)-VOLdiff (AC) DeltaTRdiff VOHdiff (AC)-VOLdiff (AC) DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test..
Differential Output Voltage(i.e. DQS-DQS)
D e lta T R d iff v O H d iff(A C )
O
v O L d iff(A C ) D e lta T F d iff
< Figure 5.4.4: Differential Output Slew Rate Definition >
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DDR3-800 Parameter Differential Output Slew Rate Symbol Min SRQdiff 5
DDR3-1066
Max
10
Min 5
Max
10
Units
V/ns
***Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting < Table 5.4.4: Differential Output Slew Rate >
5.5 Overshoot and Undershoot Specifications
5.5.1 Address and Control Overshoot and Undershoot Specifications
Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) Specification DDR3-800 0.4V 0.4V 0.67 V-ns 0.67 V-ns DDR3-1066 0.4V 0.4V 0.5 V-ns 0.5 V-ns
< Table 5.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins > < Figure 5.5.1: Address and Control Overshoot and Undershoot Definition >
Maximum Amplitude Overshoot Area
Volts (V)
VDD VSS
Undershoot Area Maximum Amplitude Time (ns)
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5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Specification DDR3-800 0.4V 0.4V 0.25 V-ns 0.25 V-ns DDR3-1066 0.4V 0.4V 0.19 V-ns 0.19 V-ns
Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure)
< Table 5.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >
M a x im u m A m p litu d e O v e rsh o o t A re a
V o lts (V )
VDDQ VSSQ
U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n
< Figure 5.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >
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5.6 Pin Capacitance
Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS, TDQS#) Input capacitance, CK and CK# Input capacitance delta CK and CK# Input capacitance (All other input-only pins) Input capacitance delta, DQS and DQS# Input capacitance delta (All CTRL input-only pins) Symbol DDR3-800 Min TBD Max TBD DDR3-1066 Min TBD Max TBD Units Notes
CIO CCK CDCK CI CDDQS CDI_CTRL
pF
1,2,3
TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD
pF pF pF pF pF pF pF
2,3,5 2,3,4 2,3,6 2,3,12 2,3,7,8 2,3,9, 10 2,3,11
Input capacitance delta CDI_ADD_ (All ADD/CMD input-only pins) CMD Input/output capacitance delta (DQ, DM, DQS, DQS#) Notes: CDIO
1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic characterization of TDQS/TDQS# should be close as much as possible, Cio & Cdio requirement is applied (recommend deleting note or changing to "Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.") 2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)") with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK#. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Absolute value of CIO(DQS) - CIO(DQS#)
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5.7 IDD Specifications (TCASE: 0 to 95oC)
4GB, 512M x 64 SO-DIMM: HMT451S6MMP8C Symbol DDR3 800 DDR3 1066 Unit note
IDD0 IDD1 IDD2N IDD2NT IDD2QNT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7
1152 1320 848 864 1232 208 400 832 912 512 1680 920 1456 2488 192 192 192 2560
1376 1536 1072 1104 1264 208 528 1056 1152 672 2096 1048 1856 2704 192 192 192 2888
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8 x8
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5.7 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. * IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
*
For IDD and IDDQ measurements, the following definitions apply: * * * * * * * "0" and "LOW" is defined as VIN <= VILAC(max). "1" and "HIGH" is defined as VIN >= VIHAC(max). "FLOATING" is defined as inputs are VREF - VDD/2. Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 26. Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 26. Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 30 through Table 10 on page 36. IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
* * *
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IDD
IDDQ (optional)
VDD
RESET CK/CK CKE CS RAS, CAS, WE A, BA ODT ZQ
VDDQ
DDR3 SDRAM
DQS, DQS DQ, DM, TDQS, TDQS
RTT = 25 Ohm VDDQ/2
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above]
Application specific memory channel environment
IDDQ Test Load
Channel IO Power Simulation
IDDQ Simulation
IDDQ Simulation
Correction Channel IO Power Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK CL nRCD nRC nRAS nRP nFAW nRRD nRFC -512Mb nRFC-1 Gb nRFC- 2 Gb nRFC- 4 Gb nRFC- 8 Gb x4/x8 x16 x4/x8 x16 DDR3-800 5-5-5 2.5 5 5 20 15 5 16 20 4 4 36 44 64 120 140 DDR3-1066 7-7-7 1.875 7 7 27 20 7 20 27 4 6 48 59 86 160 187 Unit ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High IDD0 between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on page 30; Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3 on page 30); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3 on page 30 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: IDD1 High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4 on page 31; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4 on page 31); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4 page 31 Description
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Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2N Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5 on page 32 Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2NT Address, Bank Address Inputs: partially toggling according to Table 6 on page 32; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6 on page 32; Pattern Details: see Table 6 on page 32 IDDQ2NT Precharge Standby ODT IDDQ Current (optional Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current ) Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2P0 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD2P1 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) Precharge Quiet Standby Current IDD2Q CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDDQ4R Operating Burst Read IDDQ Current (optional Same definition like for IDD4R, however measuring IDDQ current instead of IDD current )
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Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, IDD3N Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5 on page 32 Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 33; Data IO: IDD4R seamless read data burst with different data between one burst and the next one according to Table 7 on page 33; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7 on page 33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7 on page 33 Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 34; Data IO: IDD4W seamless read data burst with different data between one burst and the next one according to Table 8 on page 34; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8 on page 34); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8 on page 34 Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between IDD5B REF; Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 35; Data IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 35); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9 on page 35
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Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Self-Refresh Current: Extended Temperature Range (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): ExtendIDD6ET ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Auto Self-Refresh Current (optional)f) TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); IDD6TC CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto SelfRefresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 26; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially togIDD7 gling according to Table 10 on page 36; Data IO: read data burst with different data between one burst and the next one according to Table 10 on page 36; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10 on page 36; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 36 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
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Table 3 - IDD0 Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1,2 3,4 ... nRAS ... 1*nRC+0
ACT D, D D, D PRE ACT PRE
0 1 1 0 0 0
0 0 1 0 0 0
1 0 1 1 1 1
1 0 1 0 1 0
0 0 0 0 0 0
0 0 0 0 00 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 F F
-
repeat pattern 1...4 until nRAS - 1, truncate if necessary repeat pattern 1...4 until nRC - 1, truncate if necessary repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary repeat pattern 1...4 until 2*nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
Static High
toggling
... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
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Table 4 - IDD1 Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2
ACT D, D D, D
0 1 1
0 0 1
1 0 1
1 0 1
0 0 0
0 0 0
00 00 00
0 0 0
0 0 0
0 0 0
0000000 0 0011001 1 -
repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 0 0
repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE ACT D, D D, D 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 00 00 00 00 0 0 0 0 0 0 0 0 0 F F F 0 0 0 0 repeat pattern 1...4 until nRC - 1, truncate if necessary
Static High
toggling
1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2 3 4 5 6 7 2*nRC 4*nRC 6*nRC 8*nRC 10*nRC 12*nRC 14*nRC
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 F 0
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 0 F 0 repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
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Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2 3
D D D D
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
-
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2 3
D D D D
1 1 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 F F
0000000 0
Static High
toggling
1 2 3 4 5 6 7
4-7 8-11 12-15 16-19 20-23 24-17 28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
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Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2,3 4
RD D D,D RD D D,D
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
1 0 1 1 0 1
0 0 0 0 0 0
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
000000 00 001100 11 -
Static High
toggling
5 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
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HMT451S6MMP(R)8C
Table 8 - IDD4W Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0
0
1 2,3 4
WR D D,D WR D D,D
0 1 1 0 1 1
1 0 1 1 0 1
0 0 1 0 0 1
0 0 1 0 0 1
1 1 1 1 1 1
0 0 0 0 0 0
00 00 00 00 00 00
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 F F F
000000 00 001100 11 -
Static High
toggling
5 6,7 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63
repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are FLOATING.
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HMT451S6MMP(R)8C
Table 9 - IDD5B Measurement-Loop Patterna) Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0] 0 0 0
A[10]
ODT
RAS
CKE
CAS
WE
CS
Datab)
0 1
0
1.2 3,4 5...8
REF D, D D, D
0 1 1
0 0 1
0 0 1
1 0 1
0 0 0
0 0 0
0 00 00
0 0 0
0 0 0
0 0 F
-
repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Static High
toggling
9...12 13...16 17...20 21...24 25...28 29...32 2 33...nRFC-1
a) DM must be driven LOW all the time. DQS, DQS are FLOATING. b) DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
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HMT451S6MMP(R)8C
Table 10 - IDD7 Measurement-Loop Patterna) ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 Command Sub-Loop
Cycle Number
BA[2:0]
A[15:11]
CK, CK
A[9:7]
A[6:3]
A[2:0]
A[10]
RAS
ODT
CKE
CAS
WE
CS
Datab)
0
1
2 3 4 5 6 7 8 Static High toggling 9
10
11
12 13 14 15 16 17 18 14
ACT 0 0 1 1 0 0 00 0 0 0 0 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 D 1 0 0 0 0 0 00 0 0 0 0 repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 00 0 0 F 0 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 D 1 0 0 0 0 1 00 0 0 F 0 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3 D 1 0 0 0 0 3 00 0 0 F 0 4*nRRD ... Assert and repeat above D Command until nFAW - 1, if necessary nFAW repeat Sub-Loop 0, but BA[2:0] = 4 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7 D 1 0 0 0 0 7 00 0 0 F 0 nFAW+4*nRRD ... Assert and repeat above D Command until 2* nFAW - 1, if necessary 2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 2&nFAW+2 Repeat above D Command until 2* nFAW + nRRD - 1 2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 2&nFAW+nRRD+ 2 Repeat above D Command until 2* nFAW + 2* nRRD - 1 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3 D 1 0 0 0 0 0 00 0 0 0 0 2*nFAW+4*nRRD Assert and repeat above D Command until 3* nFAW - 1, if necessary 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7 D 1 0 0 0 0 0 00 0 0 0 0 3*nFAW+4*nRRD Assert and repeat above D Command until 4* nFAW - 1, if necessary 1 2 ... nRRD nRRD+1 nRRD+2 ... 2*nRRD 3*nRRD
0
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.2 / Apr. 2009
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HMT451S6MMP(R)8C
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
Parameter REF command to ACT or REF command time Average periodic refresh interval tREFI Symbol tRFC 512Mb 1Gb 2Gb 4Gb 8Gb Units
90
110
160
300
350
ns
0 xC < TCASE < 85 xC 85 xC < TCASE < 95 xC
7.8 3.9
7.8 3.9
7.8 3.9
7.8 3.9
7.8 3.9
us us
6.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin
DDR3 800 Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CL = 6 CWL = 5 CWL = 5 Symbol min 15 15 15 52.5 37.5 Reserved 2.5 6 5 3.3 DDR3-800E 6-6-6 max 20 -- -- -- 9 * tREFI ns ns ns ns ns ns ns 1)2)3)4) 1)2)3) Unit Notes
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG)
Supported CL Settings Supported CWL Settings
nCK nCK
Rev. 0.2 / Apr. 2009
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HMT451S6MMP(R)8C
DDR3 1066 Speed Bin CL - nRCD - nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CL = 5 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6 Symbol min 13.125 13.125 13.125 50.625 37.5
DDR3-1066F 7-7-7 max 20 -- -- -- 9 * tREFI Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 < 2.5 < 2.5 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns 1)2)3)4)6) 4) 1)2)3)6) 1)2)3)4) 4) 1)2)3)4) 4) 1)2)3) Unit Note
tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
CL = 6
CL = 7
CL = 8
Supported CL Settings Supported CWL Settings
nCK nCK
Rev. 0.2 / Apr. 2009
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HMT451S6MMP(R)8C
*Speed Bin Table Notes* Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Notes: 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. `Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
Rev. 0.2 / Apr. 2009
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HMT451S6MMP(R)8C
7. DIMM Outline Diagram
7.1 512Mx64 - HMT451S6MMP8C Front View
Side
67.60mm 3.80mm max
2.0
4.00 0.10
SPD
20.0mm 6.00
Detail- A
Detail-B
pin 1 2.15 2X 1.80 0.10 21.00 1.65 0.10 3.00 39.00
30.0mm
pin 203
1.00 0.08 mm
Back View
Detail of Contacts A
0.45 0.10
Detail of Contacts B
0.3 0.15
4.00
0.20
2.55
0.3~1.0 0.60 1.00 0.05 3.00
Rev. 0.2 / Apr. 2009
2.55
40

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